As a solid-state imaging device mounted in a digital still camera, a digital video camera, or the like, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is known. In the CMOS image sensor (hereinafter referred to as CIS), a charge is generated in response to incident light through photoelectric conversion by a PD (Photodiode) formed for each pixel, the generated charge is transferred to an FD (Floating Diffusion) via a transfer transistor, and the charge is converted into electrical signals (pixel signals) in the FD, which are read.
Meanwhile, conventionally, a configuration, in which PDs are formed in the deep portion of (at a back surface side of) an Si (silicon) substrate, has been proposed in order to improve Qs (saturation charge amount) of the CIS, to form a vertical direction spectroscopy CIS where a plurality of PDs are laminated in the vertical direction, and the like. The charge generated and accumulated in the PD and read is transferred to the FD disposed at a front surface side of the Si substrate via a vertical transistor, for example, disposed in a direction perpendicular (vertical) to the Si substrate.
In a case of the above-described configuration, a distance between the PD and the FD is long, and the vertical transistor is fixed to a low voltage during charge accumulation in the PD. Therefore, it is difficult to design the overflow. For that reason, a structure, in which an overflow drain (hereinafter referred to as OFD) is provided at a back surface side of the Si substrate, has been proposed (see Patent Literature 1, for example).
FIG. 1 shows a configuration example of a CMOS image sensor including a PD and an OFD at a back surface side of an Si substrate. It should be noted that A of FIG. 1 is a cross-sectional diagram, and B of FIG. 1 shows a potential of each part of the CIS.
A CIS 10 includes a PD 12 formed at a back surface side of (in the deep portion of) an Si substrate 11, and an FD 14 formed at a front surface side of the Si substrate 11. In addition, a vertical transistor 13 is formed in a direction perpendicular (vertical) to the Si substrate 11. Further, an OFD 16 connected to the PD 12 via a potential barrier 15 is formed at the back surface side of (in the deep portion of) the Si substrate 11. The OFD 16 includes a high concentration diffusion layer whose voltage is set at the power source voltage.
Potential levels of the PD 12, the potential barrier 15, and the OFD 16 are as shown in B of FIG. 1. In a case where the charge generated and accumulated in the PD 12 are saturated, the saturated charge is discharged into the OFD 16 via the potential barrier 15.